Welcome to Jiajing Wang's Homepage

Jan. 2006~present, Ph.D. in Electrical Engineering, University of Virginia (Degree expected in Jan. 2010)

May.2005~Dec.2005, Graduate student in Computer Engineering, Virginia Polytechnic Institute and State University

Sep.2000~Jun.2003, M.S. in Electrical Engineering, Fudan University, China

Sep.1996~Jul.2000, B.S. in Electrical Engineering, East China University of Science and Technology, China

Jan.2006~present, Research Assistant, Robust Low Power VLSI Design group, University of Virginia, VA. Working on low power, variation insensitive and statistical methods for nano-scale SRAM design.

May.2007~Apr.2007, Research Intern, Freescale Semiconductor. Worked on circuits and techniques for leakage power savings on 45nm SRAM.

May 2005~Dec.2005, Research Assistant, Advanced Research Institute, Virginia Tech, VA. Implemented a visual statistical data analyzing tool in Java and C to visualize and discover hidden data structures in high-dimensional genomic datasets.

Jul.2003~Apr.2005, IC Design and Verification Engineer, Shanghai IC Design Center, Agere Systems (now merged into LSI), Shanghai, China. Worked on IC design and verification for Media Gateway chip, DDR2 Memory Controller, and Link-Layer Processor.

Jul.2000~Jun.2003, Research Assistant, ASIC & State Key Lab, Fudan University, Shanghai, China. Worked on register file and cache design.

Louis T. Rader Graduate Research Award in Electrical and Computer Engineering, UVA, 2009

Award for Excellence in Scholarship in the Sciences & Engineering, UVA, 2009

L. William Ballard Jr. Fellowship, UVA, 2008

Best student paper award at the International Conference on VLSI Design, 2008