Modern day electronic devices are reaching nanometer dimensions where atomistic effects are dominant. Present day chips have half a billion transistors, while scanning tips allow researchers to `see' and manipulate atoms and molecules to build interesting materials and devices. Fundamentally new principles are needed to understand how current flows at these nanometer length scales (1 nm ~ 10 atomic lengths), and traditional macroscopic concepts like mobility and diffusion coefficient need to be replaced by more basic concepts that require an understanding of resistance, `friction', and electron transport at their most fundamental level. Regardless of the specific form future electronic devices adopt, it is clear that we need to develop ways to describe and model the electronic properties of device structures engineered on an atomic scale. This is what our research is all about.

Traditional CAD tools for electronic conduction are based on macroscopic concepts such as mobility and diffusion and continuum approaches such as effective mass theory, that do not apply at these length scales. We are exploring the novel physics arising from quantum interference, inelastic scattering,

Next we translate the formal evolution equations into quantitative simulation tools, using a combination of computational materials science and quantum chemistry. This includes semi-empirical as well as

Finally, we combine the formal equations with numerical simulation tools to identify performance advantages and limitations of nanoscale devices, such as resonant tunneling diodes, switches, conductors, interconnects, transistors and electronic sensors made out of various materials such as silicon or SiGe, molecules, nanotubes, nanowires, spintronic or magnetic elements and silicon quantum dots. Part of our current interests involve exploring hybrid devices operating on novel principles, such as gate-tunable scattering centers for characterization and detection, conformationally gated molecules for nano-relays, molecular redox centers and motors integrated on a silicon CMOS platform for memory and heat sinking.